Passive switched-capacitor filters conforming to power constraint

ABSTRACT

Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner.

CROSS-REFERENCE TO RELATED APPLICATION

The present Application for Patent is a divisional of patent applicationSer. No. 12/366,363 entitled “PASSIVE SWITCHED-CAPACITOR FILTERSCONFORMING TO POWER CONSTRAINT” filed Feb. 5, 2009, pending, andassigned to the assignee hereof and hereby expressly incorporated byreference herein.

BACKGROUND

I. Field

The present disclosure relates generally to electronics, and morespecifically to filters.

II. Background

Filters are commonly used to filter signals to pass desired signalcomponents and to attenuate undesired signal components. Filters arewidely used for various applications such as communication, computing,networking, consumer electronics, etc. For example, in a wirelesscommunication device such as a cellular phone, filters may be used tofilter a received signal to pass a desired signal on a specificfrequency channel and to attenuate out-of-band undesired signals andnoise. For many applications, filters that occupy small area and consumelow power are highly desirable.

SUMMARY

Passive switched-capacitor (PSC) filters that may occupy smaller areaand consume less power are described herein. In one design, a PSC filtermay implement a second-order infinite impulse response (IIR) filter withtwo complex first-order IIR sections. The second-order IIR filter maynot meet a power constraint whereas each complex first-order IIR sectionmay meet the power constraint. The coefficients for the two complexfirst-order IIR sections may be determined based on the coefficients forthe second-order IIR filter, as described below. Each complexfirst-order IIR section may be implemented with a PSC filter sectioncomprising multiple capacitors and multiple switches.

In another design, a PSC filter may implement one or more complex filtersections (e.g., two complex first-order IIR sections) coupled in series.Each complex filter section includes first, second, and third sets ofcapacitors. The first set of capacitors (e.g., capacitors 1024 a and1034 a in FIG. 10) receives a real input signal and an imaginary delayedsignal, stores and shares electrical charges, and provides a realfiltered signal. The second set of capacitors (e.g., capacitors 1024 band 1034 b in FIG. 10) receives an imaginary input signal and a realdelayed signal, stores and shares electrical charges, and provides animaginary filtered signal. The third set of capacitors (e.g., capacitors1044 and 1054 in FIG. 10) receives the real and imaginary filteredsignals, stores and shares electrical charges, and provides the real andimaginary delayed signals. Each complex filter section further includesfirst, second, third and fourth sets of switches. The first set ofswitches couples the first set of capacitors to a first summing node.The second set of switches couples the second set of capacitors to asecond summing node. The third set of switches couples the third set ofcapacitors to the first summing node. The fourth set of switches couplesthe third set of capacitors to the second summing node. Each capacitorstores a value from an associated summing node when selected forcharging and shares electrical charge with other capacitors via theassociated summing node when selected for charge sharing.

In yet another design, a PSC filter may implement a finite impulseresponse (FIR) section coupled to an IIR section, which may be for acomplex first-order IIR filter. The FIR section receives and filters acomplex input signal and provides a complex filtered signal. The IIRsection receives and filters the complex filtered signal and provides acomplex output signal. The FIR and IIR sections may be implemented withtwo PSC filter sections. Each PSC filter section may include a bank ofcomplex filter sections that may be enabled in different clock cycles.

In yet another design, a PSC filter section includes first and secondcomplex filter sections and may be used for the FIR or IIR sectiondescribed above. The first complex filter section receives and filters acomplex input signal and provide a complex output signal every M clockcycles, where M is greater than one. The second complex filter sectionreceives and filters the complex input signal and provides the complexoutput signal every M clock cycles. The first and second complex filtersections may be enabled in different clock cycles. For example, withM=2, the first complex filter section may be enabled in even-numberedclock cycles, and the second complex filter section may be enabled inodd-numbered clock cycles.

Various aspects and features of the disclosure are described in furtherdetail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a second-order FIR filter.

FIG. 2 shows a PSC filter that implements the second-order FIR filter.

FIG. 3 shows a timing diagram for the PSC filter in FIG. 2.

FIG. 4 shows a block diagram of a second-order IIR filter.

FIG. 5 shows a PSC filter that implements the second-order IIR filter.

FIG. 6 shows a timing diagram for the PSC filter in FIG. 5.

FIG. 7 shows a process for designing a PSC filter with coefficientscaling.

FIG. 8 shows filtering with complex second-order IIR filters.

FIG. 9 shows a block diagram of a complex first-order IIR section.

FIG. 10 shows a PSC filter that implements the complex first-order IIRsection.

FIG. 11 shows a timing diagram for the PSC filter in FIG. 10.

FIG. 12 shows a PSC filter that implements two complex first-order IIRsections.

FIG. 13 shows a process for designing a PSC filter with decomposition.

FIG. 14 shows a complex first-order IIR section implemented with a FIRfilter bank and an IIR filter bank.

FIG. 15 shows a PSC filter that implements the IIR filter bank in FIG.14.

FIG. 16 shows a plot of pole movement due to filter bank transformation.

FIG. 17 shows a process for designing a PSC filter with filter banktransformation.

FIG. 18 shows a plot of a function affecting power constraint.

FIG. 19 shows a process for designing an IIR filter to meet powerconstraint.

FIG. 20 shows a block diagram of a wireless communication device.

DETAILED DESCRIPTION

The PSC filters described herein may be used for various types offilters such as FIR filters, IIR filters, auto regressive moving average(ARMA) filters composed of FIR and IIR sections, etc. The PSC filtersmay also implement a filter of any order, e.g., first, second, third orhigher order. Multiple PSC filter sections may be used to form morecomplex filters. For clarity, PSC filters for second-order FIR filterand for first-order and second-order IIR filters are described in detailbelow.

A PSC filter may be implemented with only capacitors and switches,without using active circuits. This may provide certain advantagesdescribed below. However, due to the passive nature of the PSC filter,not all filter transfer functions may be directly implementable with thePSC filter. The PSC filter can implement a filter transfer function thatmeets a power constraint. Various schemes to meet the power constraintare described below and are based on observation that the totalelectrical charges before and after each charge sharing operation in thePSC circuit should be keep constant. This implies that a FIR filter isimplementable if its coefficients are scaled so that they sum to 1. Foran IIR filter, several schemes for meeting the power constraint aredescribed below and include coefficient scaling, complex filter sectiondecomposition, filter bank transformation, and pole repositioning.

FIG. 1 shows a block diagram of a second-order FIR filter 100 that maybe implemented with a PSC filter. FIR filter 100 includes two delayelements 112 and 114 coupled in series, with each delay elementproviding a delay of one clock cycle. Delay element 112 receives aninput sample x(n) and provides a delayed sample x(n−1). Delay element114 receives the delayed sample x(n−1) and provides a delayed samplex(n−2). FIR filter 100 includes two FIR taps 1 and 2 for second order. Amultiplier 120 (which may be considered as being for FIR tap 0) iscoupled to the input of delay element 112. A multiplier 122 for FIR tap1 is coupled to the output of delay element 112. A multiplier 124 forFIR tap 2 is coupled to the output of delay element 114. Multipliers120, 122 and 124 multiply their samples with filter coefficients b₀, b₁and b₂, respectively. A summer 130 is coupled to the outputs of allthree multipliers 120, 122 and 124. Summer 130 sums the outputs ofmultipliers 120, 122 and 124 and provides an output sample y(n).

The output sample y(n) from FIR filter 100 may be expressed as:

y(n)=b ₀ ·x(n)+b ₁ ·x(n−1)+b ₂ ·x(n−2).  Eq (1)

A transfer function H_(FIR)(z) for FIR filter 100 in the z-domain may beexpressed as:

H _(FIR)(z)=b ₀ +b ₁ ·z ⁻¹ +b ₂ ·z ⁻²,  Eq (2)

where z^(k) denotes a delay of k clock cycles.

The filter coefficients may be defined to meet the following powerconstraint for FIR filter:

|b ₀ |+|b ₁ |+|b ₂|=1.  Eq (3)

If coefficients b₀, b₁ and b₂ do not meet the power constraint inequation (3), then the coefficients may be scaled as follows:

b ₀ ′=K _(FIR) ·b ₀,  Eq (4a)

b ₁ ′=K _(FIR) ·b ₁, and  Eq (4b)

b ₂ ′=K _(FIR) ·b ₂,  Eq (4c)

where

$K_{FIR} = \frac{1}{{b_{0}} + {b_{1}} + {b_{2}}}$

is a scaling factor.

Eq (4d)

The scaling in equation set (4) results in the scaled coefficientsmeeting the power constraint, as follows:

|b ₀ ′|−═b ₁ ′|−|b ₂′|=1.  Eq (5)

Any set of FIR filter coefficients may be scaled to meet the powerconstraint in equation (5). The power constraint may also be referred toas an absolute magnitude sum constraint. The FIR filter may beimplemented with the scaled coefficients and may generate scaled outputsample y′(n), which may be expressed as:

y′(n)=b ₀ ′·x(n)+b ₁ ′·x(n−1)+b ₂ ′·x(n−2)=K _(FIR) ·y(n).  Eq (6)

In many cases, y′(n) may be used in place of y(n). However, in caseswhere signal level plays a non-trivial role (e.g., to avoid signalsaturation), the K_(FIR) scaling factor may be increased or decreased.Active devices such as amplifiers may be used to increase K_(FIR). Aswitching pattern may be adjusted to reduce K_(FIR).

FIG. 2 shows a schematic diagram of a design of a PSC filter 200 thatimplements second-order FIR filter 100 in FIG. 1. PSC filter 200includes an input section 220 and two tap sections 230 and 240 for FIRtaps 1 and 2, respectively, of FIR filter 100. Within PSC filter 200, aninput switch 212 has one end receiving an input signal V_(in) and theother end coupled to a summing node A. A reset switch 214 is coupledbetween the summing node and circuit ground. An output switch 216 hasone end coupled to the summing node and the other end providing anoutput signal V_(out). Switches 212, 214 and 216 may be implemented withmetal oxide semiconductor (MOS) transistors or other types oftransistors or switches.

Input section 220 includes an input capacitor 224 coupled between thesumming node and circuit ground. Tap section 230 includes two switches232 a and 232 b coupled in series with two capacitors 234 a and 234 b,respectively. Both series combinations of switch 232 and capacitor 234are coupled between the summing node and circuit ground. Tap section 240includes three switches 242 a, 242 b and 242 c coupled in series withthree capacitors 244 a, 244 b and 244 c, respectively. All three seriescombinations of switch 242 and capacitor 244 are coupled between thesumming node and circuit ground.

All capacitor(s) in each section have the same capacitance/size, whichis determined by the corresponding filter coefficient. The capacitancesof the capacitors in the three sections of PSC filter 200 may be givenas:

C ₀₀ =K·b ₀′,  Eq (7a)

C ₁₀ =C ₁₁ =K·b ₁′, and  Eq (7b)

C ₂₀ =C ₂₁ =C ₂₂ =K·b ₂′,  Eq (7c)

where C_(ij) is the capacitance of the j-th capacitor in the section forFIR tap i, and

K is a scaling constant.

As shown in equation set (7), the size of each capacitor C_(ij) isproportional to the corresponding scaled coefficient b_(i)′. K may beselected based on various factors such as switching settling time,capacitor size, power dissipation, noise, etc. A negative capacitor fora negative coefficient may be obtained by switching the polarity of thecapacitor between a read phase and a charge sharing phase.

In each clock cycle, switch 212 is closed for a brief period of time tocharge one capacitor in each section with the V_(in) signal. Thecapacitor selected for charging in each tap section is determined byswitches 232 and 242, as described below. The total input capacitanceobserved by the V_(in) signal for the charge operation may be expressedas:

C _(in) =C ₀₀ +C _(1u) +C _(2v),  Eq (8)

where uε{0, 1} is an index of the capacitor selected for charging in tapsection 230, and

vε{0, 1, 2} is an index of the capacitor selected for charging in tapsection 240.

Since the capacitors in each tap section have the same capacitance, thetotal input capacitance C_(in) is constant for each clock cycle.

In each clock cycle, an appropriate capacitor in each tap section isused to generate the V_(out) signal. For FIR tap L, the capacitorcharged L clock cycles earlier and storing x(n−L) is selected for usevia its associated switch. The two selected capacitors in tap sections230 and 240 and input capacitor 224 are used in a charge sharingoperation that implements the multiplications with filter coefficientsb₀′ through b₂′ and the summing of the multiplier outputs in equation(6).

The charge sharing operation uses capacitor size to achievemultiplication with a filter coefficient and current summing to achievesumming of the multiplier outputs. For each capacitor within PSC filter200, the voltage V_(ij) across that capacitor is determined by theV_(in) signal at the time the capacitor is charged, or V_(ij)=V_(in).The electrical charge Q_(ij) stored by each capacitor is determined bythe voltage V_(ij) across that capacitor and the capacitance C_(ij) ofthe capacitor, or Q_(ij)=V_(ij)·C_(ij). In each clock cycle, onecapacitor storing the proper sample x(n−i) from each tap section isselected, and the charges from all selected capacitors as well as inputcapacitor 224 are shared. The charge sharing for the FIR filter may beexpressed as:

$\begin{matrix}{{V_{out} = \frac{{C_{00} \cdot V_{00}} + {C_{1p} \cdot V_{1p}} + {C_{2q} \cdot V_{2q}}}{C_{00} + C_{1p} + C_{2q}}},} & {{Eq}\mspace{14mu} (9)}\end{matrix}$

where pε{0, 1} is an index of the capacitor storing x(n−1) in tapsection 230, and

qε{0, 1, 2} is an index of the capacitor storing x(n−2) in tap section240.

Since the capacitors in each tap section have the same capacitance, thetotal output capacitance C_(out) observed by the V_(out) signal isconstant for each clock cycle and is equal to the total inputcapacitance, or C_(out)=C_(in).

Index p can cycle between 0 and 1, so that in each clock cycle onecapacitor 234 in tap section 230 is charged, and the other capacitor 234is used for charge sharing. Index q can cycle from 0 through 2, so thatin each clock cycle one capacitor 244 in tap section 240 is charged, andanother capacitor 244 is used for charge sharing. PSC filter 200 may beconsidered as having six states for the six different (p, q)combinations.

FIG. 3 shows a timing diagram of various control signals for PSC filter200 in FIG. 2. A clock signal CLK is shown at the top of the timingdiagram. Control signals for the switches within PSC filter 200 areshown below the clock signal.

In the design shown in FIG. 3, each clock cycle includes a read/chargephase, a compute/charge sharing phase, a write/output phase, and areset/discharge phase. For the read phase from time T₀ to time T₁, theS_(in) control signal is asserted, switch 212 is closed, and inputcapacitor C₀₀ and one capacitor in each tap section are charged with theV_(in) signal. The S_(ij) control signal for each capacitor selected forcharging is asserted during the read phase and de-asserted at time T₂.For the charge sharing phase starting at time T₃, the S_(ij) controlsignal for each capacitor selected for charge sharing is asserted, andthe selected capacitors in sections 230 and 240 as well as capacitor C₀₀perform charge sharing via the summing node. For the write phase fromtime T₄ to time T₅, the S_(out) control signal is asserted, switch 216is closed, and the voltage at the summing node is provided as theV_(out) signal. For the reset phase from time T₆ to time T₇, theS_(reset) control signal is asserted, switch 214 is closed, and thecapacitors used for charge sharing are reset/discharged. Thesecapacitors may be charged with the V_(in) signal in the next clockcycle.

FIG. 4 shows a block diagram of a second-order IIR filter 400 that maybe implemented with a PSC filter. Within IIR filter 400, a multiplier420 receives and scales an input sample x(n) with a filter coefficientc₀. A summer 430 subtracts the output of a summer 432 from the output ofmultiplier 420 and provides an output sample y(n).

Two delay elements 412 and 414 are coupled in series, with each delayelement providing a delay of one clock cycle. Delay element 412 receivesthe output sample y(n) and provides a delayed sample y(n−1). Delayelement 414 receives delayed sample y(n−1) and provides a delayed sampley(n−2). IIR filter 400 includes two IIR taps 1 and 2 for second order. Amultiplier 422 for IIR tap 1 is coupled to the output of delay element412. A multiplier 424 for IIR tap 2 is coupled to the output of delayelement 414. Multipliers 422 and 424 multiply their samples with filtercoefficients c₁ and c₂, respectively, for the two IIR taps. Summer 432sums the outputs of multipliers 422 and 424 and provides its output tosummer 430.

The output sample y(n) from IIR filter 400 may be expressed as:

y(n)=c ₀ ·x(n)−c ₁ ·y(n−1)−c ₂ ·y(n−2).  Eq (10)

A transfer function H_(HIR)(z) for IIR filter 400 may be expressed as:

$\begin{matrix}{{H_{IIR}(z)} = {\frac{c_{0}}{1 + {c_{1} \cdot z^{- 1}} + {c_{2} \cdot z^{- 2}}}.}} & {{Eq}\mspace{14mu} (11)}\end{matrix}$

FIG. 5 shows a schematic diagram of a design of a PSC filter 500 thatimplements second-order IIR filter 400 in FIG. 4. PSC filter 500includes an input section 520 and two tap sections 530 and 540 for IIRtaps 1 and 2, respectively, of IIR filter 400. Within PSC filter 500, aninput switch 512 has one end receiving an input signal V_(in) and theother end coupled to a summing node A. A reset switch 514 is coupledbetween the summing node and circuit ground. An output switch 516 hasone end coupled to the summing node and the other end providing anoutput signal V_(out),

Input section 520 includes a capacitor 524 coupled between the summingnode and circuit ground. Tap section 530 includes a switch 532 coupledin series with a capacitor 534, the combination of which is coupledbetween the summing node and circuit ground. Tap section 540 includestwo switches 542 a and 542 b coupled in series with two capacitors 544 aand 544 b, respectively. Both series combinations of switch 542 andcapacitor 544 are coupled between the summing node and circuit ground.Capacitors 534 and 544 in tap sections 530 and 540 may be reset at thestart of filtering operation.

All capacitor(s) in each section of PSC filter 500 have the samecapacitance, which is determined by the corresponding filtercoefficient. The capacitances of the capacitors in the three sections ofPSC filter 500 may be given as:

C ₀₀ =K·c ₀,  Eq (12a)

C ₁₀ =K·c ₁, and  Eq (12b)

C ₂₀ =C ₂₁ =K·c ₂.  Eq (12c)

As shown in equation set (12), the size of each capacitor C_(ij) isproportional to the magnitude of the corresponding filter coefficientc_(i). A negative capacitor for a negative coefficient may be obtainedby switching the polarity of the capacitor between the read phase andthe charge sharing phase.

In each clock cycle, switch 512 is closed for a brief period of time tocharge capacitor 524 in section 520 with the V_(in) signal. The totalinput capacitance observed by the V_(in) signal is thus C_(in)=C₀₀, andno extra capacitors are needed for C_(in).

In each clock cycle, an appropriate capacitor in each tap section isused to generate the V_(out) signal. For IIR tap L, the capacitorcharged L clock cycles earlier and storing y(n−L) is selected for usevia its associated switch. Two selected capacitors in tap sections 530and 540 as well as input capacitor 524 are used in a charge sharingoperation that implements the multiplications with filter coefficientsc₀ through c₂ and the summing of the multiplier outputs in equation(10). The charge sharing for the IIR filter may be expressed as:

$\begin{matrix}{{V_{out} = \frac{{C_{00} \cdot V_{00}} + {C_{10} \cdot V_{10}} + {C_{2k} \cdot V_{2k}}}{C_{00} + C_{10} + C_{2k}}},} & {{Eq}\mspace{14mu} (13)}\end{matrix}$

where kε{0, 1} is an index of the capacitor storing y(n−2) in tapsection 540.

After completing the charge sharing, the voltage across capacitors C₀₀,C₁₀ and C_(2k) corresponds to y(n). Capacitors C₁₀ and C_(2k) may storey(n) for use in subsequent clock cycles. Capacitor C₀₀ may provide y(n)for the V_(out) signal. The total output capacitance observed by theV_(out) signal is C_(out)=C₀₀, and no extra capacitors are needed forC_(out).

Index k can cycle between 0 and 1, so that each capacitor 544 in tapsection 540 is used for charge sharing in alternating clock cycle. PSCfilter 500 may be considered as having two states for the two possiblevalues of k.

FIG. 6 shows a timing diagram of various control signals for PSC filter500 in FIG. 5. The clock signal CLK is shown at the top of the timingdiagram. Control signals for the switches within PSC filter 500 areshown below the clock signal.

In the design shown in FIG. 6, each clock cycle includes a read phase, acharge sharing phase, a write phase, and a reset phase. For the readphase from time T₀ to time T₁, the S_(in) control signal is asserted,switch 512 is closed, and input capacitor C₀₀ is charged with the V_(in)signal. For the charge sharing phase from time T₂ to time T₃, the S_(ij)control signal for each capacitor selected for charge sharing isasserted, and the selected capacitors as well as input capacitor C₀₀perform charge sharing via the summing node. At the end of the chargesharing phase, the S_(ij) control signal for each selected capacitor isde-asserted at time T₃, which then causes that capacitor to store y(n).For the write phase from time T₄ to time T₅, the S_(out) control signalis asserted, switch 516 is closed, and capacitor C₀₀ provides y(n) tothe V_(out) signal. For the reset phase from time T₆ to time T₇, theS_(reset) control signal is asserted, switch 514 is closed, andcapacitor C₀₀ is reset.

The coefficients for the second-order IIR filter may be defined to meetthe following power constraint for IIR filter:

|c ₀ |+|c ₁ |+|c ₂|=1.  Eq (14)

If coefficients c₀, c₁ and c₂ do not meet the power constraint inequation (14), then several schemes may be used meet the powerconstraint.

In a first scheme for meeting the power constraint for IIR filter, if|c₁|+|c₂|<1, then a scaled coefficient c₀′ may be computed as follows:

c ₀′=1|c ₁ |c ₂|.  Eq (15)

The coefficients c₀′, c₁ and c₂ meet the power constraint for IIRfilter, as follows:

|c _(0′) |+|c ₁ |+|c ₂|=1.  Eq (16)

The IIR filter may be implemented with coefficients c₀′, c₁ and c₂ andmay generate output sample y′(n), which may be expressed as:

y′(n)=c ₀ ′·x(n)−c ₁ ·y(n−1)−c ₂ ·y(n−2).  Eq (17)

The transfer function with coefficients c₀′, c₁ and c₂ may be expressedas:

$\begin{matrix}{{H_{IIR}^{\prime}(z)} = {{\frac{c_{0}^{\prime}}{c_{0}} \cdot {H_{IIR}(z)}} = {\frac{1 - {c_{1}} - {c_{2}}}{c_{0}} \cdot {{H_{IIR}(z)}.}}}} & {{Eq}\mspace{14mu} (18)}\end{matrix}$

FIG. 7 shows a process 700 for designing a PSC filter with coefficientscaling to meet the power constraint. Multiple coefficients for a filtertransfer function may be obtained (block 712). At least one of themultiple coefficients may be scaled based on a power constraint for thePSC filter (block 714). The PSC filter may then be implemented based onthe at least one scaled coefficient to obtain the filter transferfunction (block 716).

In one design, the filter transfer function may be for a FIR filter,e.g., a second-order FIR filter having the power constraint shown inequation (3). In this design, a scaling factor K_(FIR) may be determinedbased on the magnitude of each of the multiple coefficients, e.g., asshown in equation (4d). Each of the multiple coefficients may then bescaled based on the scaling factor to obtain a corresponding scaledcoefficient, e.g., as shown in equations (4a) through (4c).

In another design, the filter transfer function may be for an IIRfilter, e.g., a second-order IIR filter having the power constraintshown in equation (14). In this design, one of the multiple coefficientsmay be replaced with a new coefficient determined based on magnitude ofeach remaining coefficient, e.g., as shown in equation (15).

In a second scheme for meeting the power constraint for IIR filter, if|c₁|+|c₂|≧1, then the second-order IIR filter may be decomposed into twofirst-order IIR sections. Lower-order IIR sections often (but notalways) result in smaller coefficients, which may allow the powerconstraint to be met.

The decomposition of a second-order FIR section may be expressed as:

$\begin{matrix}{\mspace{616mu} {{Eq}\mspace{14mu} (19)}} & \; \\\begin{matrix}{{1 + {c_{1} \cdot z^{- 1}} + {c_{2} \cdot z^{- 2}}} = {\left( {1 - {p \cdot z^{- 1}}} \right) \cdot \left( {1 - {p^{*} \cdot z^{- 1}}} \right)}} \\{= {\left( {1 - {\left( {p_{re} + {j\; p_{im}}} \right) \cdot z^{- 1}}} \right) \cdot \left( {1 - {\left( {p_{re} - {j\; p_{im}}} \right) \cdot z^{- 1}}} \right)}}\end{matrix} & \;\end{matrix}$

where p=p_(re)+j p_(im) is a complex coefficient, c₁=2p_(re), c₂=p_(re)²+p_(im) ², and “*” denotes a complex conjugate.

As shown in equation (19), the decomposition of a second-order FIRsection typically produces two complex first-order FIR sections withconjugated coefficients p and p*.

The complex coefficient may be tested for the following power constraintcondition:

|p _(re) |+|p _(im)|<1.  Eq (20)

If the condition in equation (20) is satisfied, then the second-orderIIR filter in equation (10) may be implemented with two concatenatedcomplex first-order IIR sections, both of which meet the powerconstraint. A complex output sample y′(n) from the first complexfirst-order IIR section may be expressed as:

y _(re)′(n)={tilde over (c)} ₀ ^(·x) _(re)(n)+p _(re) ·y _(re)′(n−1)−p_(im) ·y _(im)′(n−1), and  Eq (21a)

y _(im)′(n)= c ₀ ·x _(im)(n)+p _(re) ·y _(im)′(n−1)+p _(im) ·y_(re)′(n−1),  Eq (21b)

where x(n)=x_(re)(n)+j x_(im) (n) is a complex input sample,

y′(n)=y_(re)′(n)+j y_(im)′(n) is a complex output sample from the firstsection, and

{tilde over (c)}₀ is a scaled coefficient that may be given as:

c ₀=1−|p _(re) |−|p _(im)|.  Eq (22)

A complex output sample y″(n) from the second complex first-order IIRsection may be expressed as:

y _(re)″(n)={tilde over (c)} ₀ ·y _(re)′(n)+p _(re) ·y _(re)″(n−1)+p_(im) ·y _(im)″(n−1), and  Eq (23a)

y _(im)″(n)={tilde over (c)} ₀ ·y _(im)′(n)+p _(re) ·y _(im)″(n−1)−p_(im) ·y _(re)″(n−1),  Eq (23b)

where y″(n)=y_(re)″(n)+j y_(im)″(n) is a complex output sample from thesecond section.

As shown in equation sets (21) and (23), the first and second complexfirst-order IIR sections have the same coefficients. The only differencein the two complex first-order IIR sections is the sign of the samplesscaled by p_(im).

As an example, a second-order IIR filter may have coefficients c₀=1,c₁=−0.25 and c₂=0.75. Since |c₁|+|c₂|=1, the first scheme for scalingcoefficients does not apply. Using the second scheme, second-order IIRfilter may be decomposed into two complex first-order IIR sections withp_(re)=0.125, p_(im)=0.857, and {tilde over (c)}₀=0.018. Since|p_(re)|+|p_(im)|<1, the two complex first-order IIR sections meet thepower constraint.

FIG. 8 shows filtering of complex input samples with complexsecond-order IIR filters 810 and 830. For IIR filter 810, real inputsamples x(n) may be filtered with a real second-order IIR filter 820 a,e.g., as shown in equation (10), to obtain real output samplesy_(re)(n). Imaginary input samples x_(im)(n) may be filtered with a realsecond-order IIR filter 820 b to obtain imaginary output samplesy_(im)(n). IIR filters 820 a and 820 b independently filter the real andimaginary parts of the complex input samples. IIR filters 820 a and 820b are identical and have the same coefficients. However, IIR filters 820a and 820 b may not meet the power constraint and thus may not bedirectly implementable.

For IIR filter 830, the complex input samples x_(re)(n) and x_(im)(n)may be filtered with a complex first-order IIR section 840 a, e.g., asshown in equation set (21), to obtain complex filtered samplesy_(re)′(n) and y_(im)′(n). The complex filtered samples may be furtherfiltered with a complex first-order IIR section 840 b, e.g., as shown inequation set (23), to obtain complex output samples y_(re)″(n) andy_(im)″(n).

IIR filter 810 composed of two real second-order IIR filters 820 a and820 b for the real and imaginary parts is equivalent to IIR filter 830composed of two complex first-order IIR sections 840 a and 840 b. Thecomplex output samples y_(re)″(n) and y_(im)″(n) from IIR filter 830 areequivalent to the complex output samples y_(re)(n) and y_(in)(n) fromIIR filter 810. However, complex first-order IIR sections 840 a and 840b may be implementable whereas real second-order IIR filters 820 a and820 b may not be implementable.

FIG. 9 shows a block diagram of complex first-order IIR section 840 a,which includes an IIR section 910 a for the real part and an IIR section910 b for the imaginary part. Within IIR section 910 a, a multiplier 920a receives and scales a real input sample x_(re)(n) with filtercoefficient {tilde over (c)}₀. A summer 930 a sums the output ofmultiplier 920 a with the output of a summer 932 a and provides a realoutput sample y_(re)′(n). A delay element 912 a receives the real outputsample y_(re)′(n) and provides a real delayed sample y_(re)′(n−1). Amultiplier 922 a for IIR tap A is coupled to the output of delay element912 a. A multiplier 924 a for IIR tap B is also coupled to the output ofdelay element 912 a. Multipliers 922 a and 924 a multiply the realdelayed sample y_(re)′(n−1) with filter coefficients p_(re) and p_(im),respectively, for IIR taps A and B. Summer 932 a subtracts the output ofa multiplier 924 b in IIR section 910 b from the output of multiplier922 a in IIR section 910 a and provides its output to summer 930 a.

IIR section 910 b includes all of the elements in IIR section 910 a. Theelements in IIR section 910 b are coupled in the same way as theelements in IIR section 910 a with the following differences. Amultiplier 922 b for IIR tap C and a multiplier 924 b for IIR tap Dmultiply the imaginary delayed sample y_(im)′(n−1) from a delay element912 b with filter coefficients p_(re) and p_(im), respectively. A summer932 b sums the output of multiplier 924 a in IIR section 910 a with theoutput of multiplier 922 b in IIR section 910 b and provides its outputto a summer 930 b.

Complex first-order IIR section 840 b in FIG. 8 may be implemented insimilar manner as complex first-order IIR section 840 a in FIG. 8, withthe difference being a swamp in the signs of the outputs of multipliers924 a and 924 b.

FIG. 10 shows a schematic diagram of a design of a PSC filter 1000 thatimplements complex first-order IIR section 840 a in FIGS. 8 and 9. PSCfilter 1000 includes a path 1010 a for the real part and a path 1010 bfor the imaginary part. Path 1010 a includes an input section 1020 a anda tap section 1030 a for IIR tap A of IIR section 840 a in FIG. 9. Path1010 b includes an input section 1020 b and a tap section 1030 b for IIRtap C in FIG. 9. Both paths 1010 a and 1010 b share a tap section 1040for IIR taps B and D in FIG. 9.

Within path 1010 a, an input switch 1012 a has one end receiving a realinput signal V_(in,re) and the other end coupled to a summing node A. Areset switch 1014 a is coupled between summing node A and circuitground. An output switch 1016 a has one end coupled to summing node Aand the other end providing a real output signal V_(out,re). Switches1012 b, 1014 b and 1016 b in path 1010 b are coupled in similar manneras switches 1012 a, 1014 a and 1016 a, respectively, in path 1010 a.

Input section 1020 a includes a capacitor 1024 a coupled between summingnode A and circuit ground. Tap section 1030 a includes a switch 1032 acoupled in series with a capacitor 1034 a, the combination of which iscoupled between summing node A and circuit ground. Input section 1020 band tap section 1030 b are coupled in similar manner between summingnode B and circuit ground. Tap section 1040 includes two switches 1042 aand 1052 a having one end coupled to summing node A and the other endcoupled to capacitors 1044 and 1054, respectively. Tap section 1040further includes two switches 1042 b and 1052 b having one end coupledto summing node B and the other end coupled to capacitors 1044 and 1054,respectively. The other ends of capacitors 1044 and 1054 are coupled tocircuit ground.

The capacitances of the capacitors in PSC filter 1000 may be given as:

C ₀₀ =C ₀₁ =K·{tilde over (c)} ₀,  Eq (24a)

C ₁₀ =C ₁₁ =K·p _(re), and  Eq (24b)

C ₂₀ =C ₂₁ =K·p _(im).  Eq (24c)

For the example above with p_(re)=0.125, p_(im)=0.857, and {tilde over(c)}₀=0.018, the capacitance ratios may be given as follows:

$\begin{matrix}{{C_{00}:C_{10}};{C_{10}:C_{11}};{{C_{20}:C_{21}} = {{\overset{\sim}{c}}_{0}:{\overset{\sim}{c}}_{0}}};{p_{re}:p_{re}};{p_{im}:p_{im}}} \\{{= {0.018:0.018}};{0.125:0.125};} \\{{0.857:0.857}}\end{matrix}$

In each clock cycle, switches 1012 a and 1012 b are closed for a briefperiod of time to charge capacitor 1024 a in section 1020 a with theV_(in,re) signal and to charge capacitor 1024 b in section 1020 b withthe V_(in,im) signal. In each clock cycle, capacitor 1024 a in section1020 a, capacitor 1034 a in section 1030 b, and either capacitor 1044 or1054 in section 1040 are used in a charge sharing operation thatimplements the multiplications with filter coefficients {tilde over(c)}₀, p_(re) and p_(im) and the summing of the multiplier outputs inequation (21a). In each clock cycle, capacitor 1024 b in section 1020 b,capacitor 1034 b in section 1030 b, and either capacitor 1054 or 1044 insection 1040 are used in a charge sharing operation that implementsequation (21b). The charge sharing for the real and imaginary parts maybe expressed as:

$\begin{matrix}{{V_{{out},{re}} = \frac{{C_{00} \cdot V_{00}} + {C_{10} \cdot V_{10}} + {C_{2k} \cdot V_{2k}}}{C_{00} + C_{10} + C_{2k}}},{and}} & {{Eq}\mspace{14mu} \left( {25a} \right)} \\{{V_{{out},{im}} = \frac{{C_{01} \cdot V_{01}} + {C_{11} \cdot V_{11}} + {C_{2\overset{\_}{k}} \cdot V_{2\overset{\_}{k}}}}{C_{01} + C_{11} + C_{2\overset{\_}{k}}}},} & {{Eq}\mspace{14mu} \left( {25b} \right)}\end{matrix}$

where kε{0, 1} is an index of the capacitor storing y_(im)′(n−1) in tapsection 1040, and

k is an index of the capacitor storing y_(re)′(n−1) in tap section 1040.

After completing the charge sharing, the voltage on summing node Acorresponds to y_(re)′(n), and the voltage on summing node B correspondsto y_(im)′(n). Capacitor 1024 a may provide y_(re)′(n) for theV_(out,re) signal, and capacitor 1024 b may provide y_(im)′(n) for theV_(out,im) signal. Capacitors 1034 a may store y_(re)′(n) and capacitor1034 b may store y_(im)′(n) for use in the next clock cycle. Capacitors1044 and 1054 are used in an interleaved manner to store y_(re)′(n) andy_(im)′(n) in each clock cycle. In each even-numbered clock cycle,capacitor 1044 may be coupled to summing node A, perform charge sharing,and store the y_(re)′(n), while capacitor 1054 may be coupled to summingnode B, perform charge sharing, and store the y_(im)′(n). In eachodd-numbered clock cycle, capacitor 1044 may be coupled to summing nodeB, perform charge sharing, and store the y_(im)′(n), while capacitor1054 may be coupled to summing node A, perform charge sharing, and storethe y_(re)′(n). Capacitor 1044 may thus be coupled to summing nodes Aand B in alternating clock cycles, and capacitor 1054 may be coupled tosumming nodes B and A in alternating clock cycles. Capacitors 1044 and1054 have the same size but are interleaved in time.

FIG. 6 shows a timing diagram that may be used for the various controlsignals for PSC filter 1000 in FIG. 10. For the read phase from time T₀to time T₁, the S_(in) control signal is asserted, switches 1012 a and1012 b are closed, capacitor C₀₀ is charged with the V_(in,re) signal,and capacitor C₀₁ is charged with the V_(in,im) signal. For the chargesharing phase from time T₂ to time T₃, the S₁₀ control signal and eitherthe S₂₀ or S₂₂ control signal are asserted, and capacitor C₀₀, capacitorC₁₀ and either capacitor C₂₀ or C₂₂ perform charge sharing via summingnode A. Simultaneously, the S₁₁ control signal and either the S₂₁ or S₂₃control signal are asserted, and capacitor C₀₁, capacitor C₁₁ and eithercapacitor C₂₀ or C₂₂ perform charge sharing via summing node B. At theend of the charge sharing phase, the S_(ij) control signal for eachselected capacitor is de-asserted at time T₃, which then causes thatcapacitor to store y_(re)′(n) or y_(im)′(n). For the write phase fromtime T₄ to time T₅, the S_(out) control signal is asserted, switches1016 a and 1016 b are closed, capacitor C₀₀ provides y_(re)′(n) to theV_(out,re) signal, and capacitor C₀₁ provides y_(im)′(n) to theV_(out,im) signal. For the reset phase from time T₆ to time T₇, theS_(reset) control signal is asserted, switches 1014 a and 1014 b areclosed, and capacitors C₀₀ and C₀₁ are reset.

FIG. 11 shows a timing diagram of a switching pattern for PSC filter1000 in FIG. 10. The switching pattern includes two cycles 0 and 1 forthe two possible values of k in equation set (25) and repeats every twoclock cycles. Table 1 shows the two cycles 0 and 1 and, for each cycle,gives the capacitors used to generate the V_(out,re) and V_(out,im)signals.

TABLE 1 Cycle Capacitors used to Capacitors used to k generateV_(out, re) generate V_(out, im) 0 C₀₀, C₁₀ and C₂₀ C₀₁, C₁₁ and C₂₁ 1C₀₀, C₁₀ and C₂₁ C₀₁, C₁₁ and C₂₀

For cycle 0, input capacitor C₀₀ is charged with the V_(in,re) signaland capacitor C₀₁ is charged with the V_(in,im) signal when the S_(in)control signal is asserted during the read phase. The S₁₀, S₁₁, S₂₀ andS₂₃ control signals are asserted during the charge sharing phase,capacitors C₀₀, C₁₀ and C₂₀ are used to generate the V_(out,re) signal,and capacitors C₀₁, C₁₁ and C₂₁ are used to generate the V_(out,im)signal. Capacitors C₁₀ and C₂₀ store the V_(out,re) signal andcapacitors C₁₁ and C₂₁ store the V_(0ut,im) signal at the end of thecharge sharing phase.

For cycle 1, input capacitor C₀₀ is charged with the V_(in,re) signaland capacitor C₀₁ is charged with the V_(in,im) signal during the readphase. The S₁₀, S₁₁, S₂₁ and S₂₂ control signals are asserted during thecharge sharing phase, capacitors C₀₀, C₁₀ and C₂₁ are used to generatethe V_(out,re) signal, and capacitors C₀₁, C₁₁ and C₂₀ are used togenerate the V_(out,im) signal. Capacitors C₁₀ and C₂₁ store theV_(out,re) signal and capacitors C₁₁ and C₂₀ store the V_(out,im) signalat the end of the charge sharing phase.

For PSC filter 1000, capacitors C₀₀ and C₀₁ are charged with theV_(in,re) and V_(in,im) signals in each clock cycle and are also usedfor charge sharing in the same clock cycle. Capacitors C₁₀ and C₁₁ areused for charge sharing in each clock cycle and store y_(re)′(n) andy_(im)′(n) for use in the next clock cycle. For tap section 1040, indexk toggles between 0 and 1, capacitors C₂₀ and C₂₁ are used for chargesharing at nodes A and B in one clock cycle, at nodes B and A in thefollowing clock cycle, etc.

Table 2 summarizes the action performed by each capacitor in PSC filter1000 in each clock cycle.

TABLE 2 Clock Cycle n n + 1 n + 2 . . . Capacitor C₀₀ store x_(re)(n)store x_(re)(n + 1) store x_(re)(n + 2) . . . x_(re)(n)→ y_(re)(n)x_(re)(n + 1)→ y_(re)(n + 1) x_(re)(n + 2)→ y_(re)(n + 2) Capacitor C₀₁store x_(im)(n) store x_(im)(n + 1) store x_(im)(n + 2) . . . x_(im)(n)→y_(im)(n) x_(im)(n + 1)→ y_(im)(n + 1) x_(im)(n + 2)→ y_(im)(n + 2)Capacitor C₁₀ y_(re)(n − 1)→ y_(re)(n) y_(re)(n)→ y_(re)(n + 1)y_(re)(n + 1)→ y_(re)(n + 2) . . . store y_(re)(n) store y_(re)(n + 1)store y_(re)(n + 2) Capacitor C₁₁ y_(im)(n − 1)→ y_(im)(n) y_(im)(n)→y_(im)(n + 1) y_(im)(n + 1)→ y_(im)(n + 2) . . . store y_(im)(n) storey_(im)(n + 1) store y_(im)(n + 2) Capacitor C₂₀ y_(im)(n − 1)→ y_(re)(n)y_(re)(n)→ y_(im)(n + 1) y_(im)(n + 1)→ y_(re)(n + 2) . . . storey_(re)(n) store y_(im)(n + 1) store y_(re)(n + 2) Capacitor C₂₁ y_(re)(n− 1)→ y_(im)(n) y_(im)(n)→ y_(re)(n + 1) y_(re)(n + 1)→ y_(im)(n + 2) .. . store y_(im)(n) store y_(re)(n + 1) store y_(im)(n + 2)

FIG. 12 shows a schematic diagram of a design of a PSC filter 1200 thatimplements complex first-order IIR sections 840 a and 840 b in FIG. 8.PSC filter 1200 includes a first PSC filter section 1210 a thatimplements complex first-order IIR section 840 a and a second PSC filtersection 1210 b that implements complex first-order IIR section 840 b.Each PSC filter section 1210 includes all elements in PSC filter 1000 inFIG. 10. The capacitors in tap section 1040 within PSC filter section1210 a are selected in different order than the capacitors in tapsection 1040 within PSC filter section 1210 b due to the differencebetween equation sets (21) and (23).

FIG. 13 shows a process 1300 for designing a PSC filter withdecomposition. A filter transfer function may be decomposed intomultiple complex first-order filter sections, e.g., as shown in equation(19) (block 1312). In one design of block 1312, the filter transferfunction is for a second-order IIR filter and may be decomposed into twocomplex first-order IIR sections. Complex coefficients (e.g., p and p*)for the two complex first-order IIR sections may be determined based oncoefficients (e.g., c₁ and c₂) for the second-order IIR filter. An inputcoefficient (e.g., {tilde over (c)}₀) for the two complex first-orderIIR sections may be determined based on the magnitude of the real andimaginary parts (e.g., p_(re) and p_(im)) of the complex coefficients,e.g., as shown in equation (22). The multiple complex first-order filtersections may be implemented with multiple PSC filter sections to obtainthe filter transfer function (block 1314).

The two complex first-order IIR sections obtained by decomposing asecond-order IIR filter may not meet the power constraint. The complexpole obtained from the decomposition may be expressed as:

p=p _(re) +jp _(in) =r·e ^(jθ),  Eq (26)

where r is the magnitude of the pole and θ is the phase of the pole.

The sum of the magnitude of the real and imaginary parts of the pole maybe expressed as:

|p _(re) |+|p _(im) |=r·(|cos θ|+|sin θ|).  Eq (27)

A necessary and sufficient condition for stability of an IIR filter isr<1. The power constraint may be met with |p_(re)|+|p_(im)|<1. The term(|cos θ|+|sin θ|) may be greater than one depending on the value of θ.Thus, it is possible to have |p_(re)|+|p_(im)|≧1 even with r<1, in whichcase the IIR filter is stable but not directly implementable.

In a third scheme for meeting the power constraint for IIR filter, whichmay be used when the complex first-order IIR sections do not meet thepower constraint, a complex first-order IIR section may be implementedwith an interleaved filter bank. From equation set (21), the complexfiltered samples from complex first-order IIR section 840 a may beexpressed as:

$\begin{matrix}\begin{matrix}{{y^{\prime}(n)} = {{{\overset{\sim}{c}}_{0} \cdot {x(n)}} + {p \cdot {y^{\prime}\left( {n - 1} \right)}}}} \\{= {{{\overset{\sim}{c}}_{0} \cdot {x(n)}} + {p \cdot {\overset{\sim}{c}}_{0} \cdot {x\left( {n - 1} \right)}} + {p^{2} \cdot {{y^{\prime}\left( {n - 2} \right)}.}}}}\end{matrix} & {{Eq}\mspace{14mu} (28)}\end{matrix}$

Two consecutive filtered samples from complex first-order IIR section840 a may be expressed as:

y′(n)={tilde over (c)} ₀ ·x(n)+p·{tilde over (c)} ₀ ·x(n−1)+p ²·y′(n−2), and  Eq (29a)

y′(n+1)={tilde over (c)} ₀ ·x(n+1)+p·{tilde over (c)} ₀ ·x(n)+p ²·y′(n−1).  Eq (29b)

Equation set (29) may be partitioned into an IIR part and a FIR part.The IIR part may also be referred to as a recursive part or anautoregressive part. The FIR part may also be referred to as anon-recursive part. The IIR part may be expressed as:

y′(n)={hacek over (c)} ₀ ·{hacek over (x)}(n)+p ² ·y′(n−2), and  Eq(30a)

y′(n+1)={hacek over (c)} ₀ ·{hacek over (x)}(n+1)+p ² ·y′(n−1),  Eq(30b)

where {hacek over (c)}₀=1−|real (p²)|−|mag (p²)| and {hacek over (x)}(n)is the output of the FIR part.

The FIR part may be expressed as:

{hacek over (x)}(n)={hacek over (c)} ₀ ⁻¹ ·{tilde over (c)} ₀·x(n)+{hacek over (c)} ₀ ⁻¹ ·{tilde over (c)} ₀ ·p·x(n−1), and  Eq (31a)

{hacek over (x)}(n+1)={hacek over (c)} ₀ ⁻¹ ·{tilde over (c)} ₀·x(n+1)+{hacek over (c)} ₀ ⁻¹ ·{tilde over (c)} ₀ ·p·x(n).  Eq (31b)

FIG. 14 shows a block diagram of a complex first-order IIR section 1400implemented with a FIR filter bank 1410 and an IIR filter bank 1420. FIRfilter bank 1410 may filter the complex input samples x_(re)(n) andx_(im)(n) as shown in equation set (31) and provide complex filteredsamples {hacek over (x)}_(re)(n) and {hacek over (x)}_(im)(n). IIRfilter bank 1420 may filter the complex filtered samples {hacek over(x)}_(re)(n) and {hacek over (x)}_(im)(n) as shown in equation set (30)and provide complex output samples y_(re)′(n) and y_(im)′(n). FIG. 14shows a design with IIR filter bank 1420 being placed after FIR filterbank 1410. In another design, FIR filter bank 1410 may be placed afterIIR filter bank 1420. The order of FIR filter bank 1410 and IIR filterbank 1420 may be selected based on noise and other considerations.

FIG. 15 shows a schematic diagram of a design of a PSC filter 1500 thatimplements IIR filter bank 1420 in FIG. 14. PSC filter 1500 includes afirst IIR section 1510 a and a second IIR section 1510 b. Each IIRsection 1510 includes all elements of PSC filter 1000 in FIG. 10.

A real input signal V_(in,re) is provided to both a switch 1512 a in IIRsection 1510 a and a switch 1512 c in IIR section 1510 b. An imaginaryinput signal V_(in,im) is provided to both a switch 1512 b in IIRsection 1510 a and a switch 1512 d in IIR section 1510 b. A switch 1516a in IIR section 1510 a and a switch 1516 c in IIR section 1510 b arecoupled together and provide a real output signal V_(out,re). A switch1516 b in IIR section 1510 a and a switch 1516 d in IIR section 1510 bare coupled together and provide an imaginary output signal V_(out,im).The other elements within IIR sections 1510 a and 1510 b are coupled asdescribed above for FIG. 10.

IIR section 1510 a operates in each even-numbered clock cycle, filtersthe V_(in,re) and V_(in,im) signals, and provides the V_(out,re) andV_(out,im) signals. IIR section 1510 a is disabled during eachodd-numbered clock cycle. Conversely, IIR section 1510 b operates ineach odd-numbered clock cycle, filters the V_(in,re) and V_(in,im)signals, and provides the V_(out,re) and V_(out,im) signals. IIR section1510 b is disabled during each even-numbered clock cycle. IIR sections1510 a and 1510 b thus operate in an interleaved manner, with IIRsection 1510 a operating in one clock cycle, then IIR section 1510 boperating in the next clock cycle, then IIR section 1510 a operating inthe following clock cycle, etc. IIR section 1510 a operates on {hacekover (x)}(n) and provides y′(n), as shown in equation (30a). IIR section1510 b operates on {hacek over (c)}(n+1) and provides y′(n+1), as shownin equation (30b).

In one design, a PSC filter for FIR filter bank 1410 in FIG. 14 (whichmay be a FIR filter) may be implemented in similar manner as PSC filter1000 in FIG. 10. However, the switches for the PSC filter for FIR filterbank 1410 are operated to implement a FIR filter instead of an IIRfilter. In another design, two FIR filter banks may be merged from twofirst-order complex IIR filters. The merged second-order FIR filter hasreal coefficients and may be implemented as a normal second-order PSCFIR filter.

Equation sets (30) and (31) show filter bank transformation for a casein which IIR filter bank 1420 includes two IIR sections. In general, thefilter bank transformation may be performed for any value of m orM=2^(m) to obtain a complex pole at p² ^(m) =p^(M). The IIR part may beexpressed as:

y′(n+i)={hacek over (c)} ₀ ·{hacek over (x)}(n+i)+p ^(M) ·y′(n−M+i), fori=0, . . . , M−1,  Eq (32)

where {hacek over (c)}₀=1−|real (p ^(M))|−|imag (p ^(M))|.  Eq (33)

A filter bank may thus include M IIR sections. Each IIR section may beimplemented as shown in FIG. 15, may operate at 1/M of the clock rate,and may be enabled every M clock cycles. The M IIR sections may besequentially enabled in M clock cycles, one IIR section in each clockcycle.

FIG. 16 shows a plot 1610 of pole movement due to filter banktransformation with different values of M. An IIR filter is stable ifits pole has a magnitude of r<1 and is located within a unit circle1612. The pole of the IIR filter meets the power constraint in equation(20) if it is located within a diamond box 1614. The filter banktransformation changes the pole from p to p^(M). Plot 1610 shows thepole location for an example IIR filter with c₀=1, c₁=1.5 and c₂=0.6875.In this example, the pole p obtained from decomposition is locatedoutside diamond box 1614 and thus does not meet the power constraint.The filter bank transformation with M=2 results in the pole p² beinglocated within diamond box 1614 and thus meets the power constraint. Thefilter bank transformation with M=4 and 8 results in the poles p⁴ and p⁸being located closer to the origin. As shown by this example, the polegenerally moves toward the origin for larger values of M. In general, alarger distance from the pole to the unit circle may result in smallerinsertion loss, which is desirable.

The pole due to filter bank transformation with M=2 may be expressed as:

p ² =r ² ·e ^(j2θ) ≡{hacek over (p)}={hacek over (p)} _(re) +j{hacekover (c)} _(im).  Eq (34)

The power constraint for the IIR part may then be expressed as:

|{hacek over (p)}_(re) |+|{hacek over (p)} _(im) |=r ²·(|cos 2θ|+|sin2θ|)≦1.  Eq (35)

Since r<1 for a stable IIR filter, r²<r and it may be more possible tomeet the power constraint. As an example, a complex first-order IIRsection with pole of p=0.625+j 0.625 does not meet the power constraint.However, a filter bank with pole of p²=j 0.78 meets the powerconstraint.

Equation (35) is for a 2-way interleaved filter bank with M=2. Ingeneral, the power constraint for an M-way interleaved filter bank maybe expressed as:

|{hacek over (p)}_(re) |+|{hacek over (p)} _(im) |−r ^(M)·(|cosM·θ|+|sin M·θ|)≦1.  Eq (36)

In theory, the power constraint can always be satisfied if M issufficiently large. However, a larger M also corresponds to greatercomplexity for the IIR part.

FIG. 17 shows a process 1700 for designing a PSC filter with filter banktransformation. A filter transfer function may be decomposed into a FIRpart and an IIR part (block 1712). In one design, the filter transferfunction is for a complex first-order IIR filter and may be decomposedinto the FIR part and the IIR part. A complex coefficient (e.g., p^(M))for the IIR part may be determined based on a complex coefficient (e.g.,p) for the complex first-order IIR filter. The IIR part may bepartitioned into multiple (M) IIR sections, with each IIR sectionoperating at 1/M clock rate, and the M IIR sections being sequentiallyenabled in M clock cycles (block 1714). In one design, the IIR part maybe partitioned into first and second IIR sections, with the first IIRsection being enabled in even-numbered clock cycles, and the second IIRsection being enabled in odd-numbered clock cycles. The FIR and IIRparts may be implemented with PSC filter sections to obtain the filtertransfer function (block 1716).

In a fourth scheme for meeting the power constraint for IIR filter, polerepositioning may be performed, and a pole may be moved to a moresuitable location in order to meet the power constraint. The second partof the right hand side of equation (22) may be expressed as:

f(θ)=(|cos θ|+|sin θ|).  Eq (37)

FIG. 18 shows a plot 1810 of function f(θ) in equation (37). Functionf(θ) has a minimum value of 1.0 for θ=i·π/2, where i is an integer. Inorder to meet the power constraint |p_(re)|+|p_(im)|<1, it is better tominimize f(θ), which means making either θ or M·θ close to i·π/2. It maybe desirable to have θ≈π/2, so that the poles are on the imaginary axis.If the interleaved filter bank with M=2 is used, then it may bedesirable to have θ≈π/4 or θ≈3π/4. This may be achieved by a multi-ratefilter design.

For the fourth scheme, the pole location may be varied in a systematicor pseudo-random manner. The pole at each new location may be evaluatedto determine whether (i) a desired filter response can be obtained withthe new pole location and (ii) the power constraint is met with the newpole location.

FIG. 19 shows a process 1900 for designing a second-order IIR filter tomeet power constraint. The second-order IIR filter may be designed tomeet applicable system requirements. The coefficients c₀, c₁ and c₂ ofthe second-order IIR filter may be obtained (block 1912). Adetermination is made whether the coefficients can be scaled, e.g.,whether |c₁|+|c₂|<1 (block 1914). If the answer is ‘Yes’ for block 1914,then coefficient scaling may be performed to obtain coefficient c₀′ asshown in equation (15) (block 1924). Otherwise, the second-order IIRfilter may be decomposed into complex first-order IIR sections (block1916). A determination is made whether the pole of the first-order IIRsections meet the power constraint, e.g., whether |p_(re)|+|p_(im)|<1(block 1918). If the answer is ‘Yes’ for block 1918, then coefficientscaling may be performed to obtain coefficient {hacek over (c)}₀ asshown in equation (22) (block 1924).

Otherwise, each complex first-order IIR section may be implemented witha filter bank starting with m=1 (block 1920). A determination is madewhether the pole for the filter bank meets the power constraint, e.g.,whether |{hacek over (p)}_(re)|+|{hacek over (p)}_(im)|<1 (block 1922).If the answer is ‘Yes’ for block 1922, then coefficient scaling may beperformed to obtain coefficient {hacek over (c)}₀ as shown in equation(33) (block 1924). Otherwise, a determination is made whether m is equalto a maximum value (block 1926). If the answer is ‘No’, then m may beincremented (block 1928), and the process may then return to block 1920.Otherwise, pole repositioning may be performed in order to meet thepower constraint (block 1930).

For clarity, much of the description above is for second-order FIRfilter and first-order and second-order IIR filters. The PSC filtersdescribed herein may be used for FIR filters and IIR filters of anyorder.

The PSC filters described herein may provide certain advantages. First,the PSC filters do not utilize amplifiers within the PSC filters, whichmay reduce size and power consumption. Amplifiers may be used forinput/output buffering. Second, the PSC filters may be able to providean accurate frequency response, which is determined by capacitor ratiosthat can be more accurately achieved in an integrated circuit (IC).Third, the PSC filters may have high adaptability since it uses an arrayof capacitors that may be configured during operation, e.g., to obtaindifferent filter responses.

The PSC filters described herein may be used for various applicationssuch as wireless communication, computing, networking, consumerelectronics, etc. The PSC filters may also be used for various devicessuch as wireless communication devices, cellular phones, broadcastreceivers, personal digital assistants (PDAs), handheld devices,wireless modems, laptop computers, cordless phones, Bluetooth devices,wireless local loop (WLL) stations, consumer electronics devices, etc.For clarity, the use of the PSC filters in a wireless communicationdevice, which may be a cellular phone or some other device, is describedbelow. The PSC filters may be used to pass a desired signal, toattenuate jammers and out-of-band noise and interference, and/or toperform other functions in the wireless device.

FIG. 20 shows a block diagram of a design of a wireless communicationdevice 2000 in which the PSC filter described herein may be implemented.Wireless device 2000 includes a receiver 2020 and a transmitter 2040that support bi-directional communication. In general, wireless device2000 may include any number of receivers and any number of transmittersfor any number of communication systems and frequency bands.

In the receive path, an antenna 2012 may receive radio frequency (RF)modulated signals transmitted by base stations and provide a received RFsignal, which may be routed through an RF unit 2014 and provided toreceiver 2020. RF unit 2014 may include an RF switch and/or a duplexerthat can multiplex RF signals for the transmit and receive paths. Withinreceiver 2020, a low noise transconductance amplifier (LNTA) 2022 mayamplify the received RF signal (which may be a voltage signal) andprovide an amplified RF signal (which may be a current signal). Apassive sampler 2024 may sample the amplified RF signal, performfrequency downconversion via a sampling operation, and provide analogsamples. An analog sample is an analog value for a discrete timeinstant. A filter/decimator 2026 may filter the analog samples, performdecimation, and provide filtered samples at a lower sample rate.Filter/decimator 2026 may be implemented with the PSC filters describedherein.

The filtered samples from filter/decimator 2026 may be amplified by avariable gain amplifier (VGA) 2028, filtered by a filter 2030, furtheramplified by an amplifier (AMP) 2032, further filtered by a filter 2034,and digitized by an analog-to-digital converter (ADC) 2036 to obtaindigital samples. Filter 2030 and/or 2034 may be implemented with the PSCfilters described herein. VGA 2028 and/or amplifier 2032 may beimplemented with switched-capacitor amplifiers that can amplify theanalog samples from filters 2026 and 2030. A digital processor 2050 mayprocess the digital samples to obtain decoded data and signaling. Acontrol signal generator 2038 may generate a sampling clock for passivesampler 2024 and control signals for filters 2026, 2030 and 2034.

In the transmit path, transmitter 2040 may process output samples fromdigital processor 2050 and provide an output RF signal, which may berouted through RF unit 2014 and transmitted via antenna 2012. Forsimplicity, details of transmitter 2040 are not shown in FIG. 20.

Digital processor 2050 may include various processing units for datatransmission and reception as well as other functions. For example,digital processor 2050 may include a digital signal processor (DSP), areduced instruction set computer (RISC) processor, a central processingunit (CPU), etc. A controller/processor 2060 may control the operationat wireless device 2000. A memory 2062 may store program codes and datafor wireless device 2000. Data processor 2050, controller/processor2060, and/or memory 2062 may be implemented on one or more applicationspecific integrated circuits (ASICs) and/or other ICs.

FIG. 20 shows a specific design of receiver 2020. In general, theconditioning of the signals within receiver 2020 may be performed by oneor more stages of mixer, amplifier, filter, etc. These circuit blocksmay be arranged differently from the configuration shown in FIG. 20.Furthermore, other circuit blocks not shown in FIG. 20 may also be usedto condition the signals in the receiver. Some circuit blocks in FIG. 20may also be omitted. All or a portion of receiver 2020 may beimplemented on one or more RF ICs (RFICs), mixed-signal ICs, etc.

The received RF signal from antenna 2012 may contain both a desiredsignal and jammers. A jammer is a large amplitude undesired signal closein frequency to a desired signal. The jammers may be attenuated prior toADC 2036 in order to avoid saturation of the ADC. Filters 2026, 2030and/or 2034 may attenuate the jammers and other out-of-band noise andinterference and may each be implemented with any of the PSC filtersdescribed herein.

The PSC filters described herein may be implemented on an IC, an analogIC, an RFIC, a mixed-signal IC, an ASIC, a printed circuit board (PCB),an electronics device, etc. The PSC filters may also be fabricated withvarious IC process technologies such as complementary metal oxidesemiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS),bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicongermanium (SiGe), gallium arsenide (GaAs), etc.

An apparatus implementing the PSC filters described herein may be astand-alone device or may be part of a larger device. A device may be(i) a stand-alone IC, (ii) a set of one or more ICs that may includememory ICs for storing data and/or instructions, (iii) an RFIC such asan RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASICsuch as a mobile station modem (MSM), (v) a module that may be embeddedwithin other devices, (vi) a receiver, cellular phone, wireless device,handset, or mobile unit, (vii) etc.

In one or more exemplary designs, the functions described may beimplemented in hardware, software, firmware, or any combination thereof.If implemented in software, the functions may be stored on ortransmitted over as one or more instructions or code on acomputer-readable medium. Computer-readable media includes both computerstorage media and communication media including any medium thatfacilitates transfer of a computer program from one place to another. Astorage media may be any available media that can be accessed by acomputer. By way of example, and not limitation, such computer-readablemedia can comprise RAM, ROM, EEPROM, CD-ROM or other optical diskstorage, magnetic disk storage or other magnetic storage devices, or anyother medium that can be used to carry or store desired program code inthe form of instructions or data structures and that can be accessed bya computer. Also, any connection is properly termed a computer-readablemedium. For example, if the software is transmitted from a website,server, or other remote source using a coaxial cable, fiber optic cable,twisted pair, digital subscriber line (DSL), or wireless technologiessuch as infrared, radio, and microwave, then the coaxial cable, fiberoptic cable, twisted pair, DSL, or wireless technologies such asinfrared, radio, and microwave are included in the definition of medium.Disk and disc, as used herein, includes compact disc (CD), laser disc,optical disc, digital versatile disc (DVD), floppy disk and blu-ray discwhere disks usually reproduce data magnetically, while discs reproducedata optically with lasers. Combinations of the above should also beincluded within the scope of computer-readable media.

The previous description of the disclosure is provided to enable anyperson skilled in the art to make or use the disclosure. Variousmodifications to the disclosure will be readily apparent to thoseskilled in the art, and the generic principles defined herein may beapplied to other variations without departing from the scope of thedisclosure. Thus, the disclosure is not intended to be limited to theexamples and designs described herein but is to be accorded the widestscope consistent with the principles and novel features disclosedherein.

What is claimed is:
 1. An apparatus comprising: a first complexfirst-order infinite impulse response (IIR) section operative to receiveand filter a complex input signal and provide a complex filtered signal;and a second complex first-order IIR section coupled to the firstcomplex first-order IIR section and operative to receive and filter thecomplex filtered signal and provide a complex output signal.
 2. Theapparatus of claim 1, wherein the first and second complex first-orderIIR sections are implemented with first and second passiveswitched-capacitor (PSC) filter sections, each PSC filter sectioncomprising a plurality of capacitors and a plurality of switches.
 3. Theapparatus of claim 1, wherein the first complex first-order IIR sectionis defined by a first complex coefficient and the second complexfirst-order IIR section is defined by a second complex coefficient, thesecond complex coefficient being a complex conjugate of the firstcomplex coefficient.
 4. An apparatus comprising: a first complex filtersection operative to receive and filter a complex input signal andprovide a complex output signal every M clock cycles, where M is greaterthan one; and a second complex filter section operative to receive andfilter the complex input signal and provide the complex output signalevery M clock cycles, the first and second complex filter sections beingenabled in different clock cycles.
 5. The apparatus of claim 4, whereinthe first complex filter section is enabled in even-numbered clockcycles and the second complex filter section is enabled in odd-numberedclock cycles.
 6. The apparatus of claim 4, wherein the first and secondcomplex filter sections each comprises a first set of capacitorsoperative to receive a real input signal and an imaginary delayed outputsignal, to store and share electrical charges, and to provide a realoutput signal, a second set of capacitors operative to receive animaginary input signal and a real delayed output signal, to store andshare electrical charges, and to provide an imaginary output signal, anda third set of capacitors operative to receive the real and imaginaryoutput signals, to store and share electrical charges, and to providethe real and imaginary delayed output signals, wherein the complex inputsignal comprises the real and imaginary input signals, and wherein thecomplex output signal comprises the real and imaginary output signals.7. An apparatus comprising: a finite impulse response (FIR) sectionoperative to receive and filter a first complex input signal and providea first complex output signal, the FIR section comprising a firstpassive switched-capacitor (PSC) filter section; and an infinite impulseresponse (IIR) section coupled to the FIR section and operative toreceive and filter a second complex input signal and provide a secondcomplex output signal, the IIR section comprising a second PSC filtersection.
 8. The apparatus of claim 7, wherein the IIR section is coupledafter the FIR section, and wherein the second complex input signalcomprises the first complex output signal.
 9. The apparatus of claim 7,wherein the FIR section is coupled after the IIR section, and whereinthe first complex input signal comprises the second complex outputsignal.
 10. The apparatus of claim 7, wherein the IIR section comprisesmultiple complex filter sections operative to receive and filter thesecond complex input signal and provide the second complex outputsignal, the multiple complex filter sections being enabled in differentclock cycles.
 11. The apparatus of claim 7, wherein the IIR section andthe FIR section implement a complex first-order IIR filter.